// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  cpu_cluster_cfg_reg_offset_field.h
// Project line  :  ICT
// Department    :  ICT Processor Chipset Development Dep
// Author        :  xxx
// Version       :  1.0
// Date          :  2015/11/15
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/19 15:33:20 Create file
// ******************************************************************************

#ifndef __CPU_CLUSTER_CFG_REG_OFFSET_FIELD_H__
#define __CPU_CLUSTER_CFG_REG_OFFSET_FIELD_H__

#define CPU_CLUSTER_CFG_ICG_EN_DBG_LEN       1
#define CPU_CLUSTER_CFG_ICG_EN_DBG_OFFSET    4
#define CPU_CLUSTER_CFG_ICG_EN_ATB_LEN       1
#define CPU_CLUSTER_CFG_ICG_EN_ATB_OFFSET    3
#define CPU_CLUSTER_CFG_ICG_EN_GIC_LEN       1
#define CPU_CLUSTER_CFG_ICG_EN_GIC_OFFSET    2
#define CPU_CLUSTER_CFG_ICG_EN_SCU_LEN       1
#define CPU_CLUSTER_CFG_ICG_EN_SCU_OFFSET    1
#define CPU_CLUSTER_CFG_ICG_EN_PERIPH_LEN    1
#define CPU_CLUSTER_CFG_ICG_EN_PERIPH_OFFSET 0

#define CPU_CLUSTER_CFG_ICG_DIS_DBG_LEN       1
#define CPU_CLUSTER_CFG_ICG_DIS_DBG_OFFSET    4
#define CPU_CLUSTER_CFG_ICG_DIS_ATB_LEN       1
#define CPU_CLUSTER_CFG_ICG_DIS_ATB_OFFSET    3
#define CPU_CLUSTER_CFG_ICG_DIS_GIC_LEN       1
#define CPU_CLUSTER_CFG_ICG_DIS_GIC_OFFSET    2
#define CPU_CLUSTER_CFG_ICG_DIS_SCU_LEN       1
#define CPU_CLUSTER_CFG_ICG_DIS_SCU_OFFSET    1
#define CPU_CLUSTER_CFG_ICG_DIS_PERIPH_LEN    1
#define CPU_CLUSTER_CFG_ICG_DIS_PERIPH_OFFSET 0

#define CPU_CLUSTER_CFG_ICG_EN_MBIST_CORE_LEN       1
#define CPU_CLUSTER_CFG_ICG_EN_MBIST_CORE_OFFSET    1
#define CPU_CLUSTER_CFG_ICG_EN_MBIST_FCM_PPU_LEN    1
#define CPU_CLUSTER_CFG_ICG_EN_MBIST_FCM_PPU_OFFSET 0

#define CPU_CLUSTER_CFG_ICG_DIS_MBIST_CORE_LEN       1
#define CPU_CLUSTER_CFG_ICG_DIS_MBIST_CORE_OFFSET    1
#define CPU_CLUSTER_CFG_ICG_DIS_MBIST_FCM_PPU_LEN    1
#define CPU_CLUSTER_CFG_ICG_DIS_MBIST_FCM_PPU_OFFSET 0

#define CPU_CLUSTER_CFG_SRST_REQ_CPU7_LEN        1
#define CPU_CLUSTER_CFG_SRST_REQ_CPU7_OFFSET     15
#define CPU_CLUSTER_CFG_SRST_REQ_CPU6_LEN        1
#define CPU_CLUSTER_CFG_SRST_REQ_CPU6_OFFSET     14
#define CPU_CLUSTER_CFG_SRST_REQ_CPU5_LEN        1
#define CPU_CLUSTER_CFG_SRST_REQ_CPU5_OFFSET     13
#define CPU_CLUSTER_CFG_SRST_REQ_CPU4_LEN        1
#define CPU_CLUSTER_CFG_SRST_REQ_CPU4_OFFSET     12
#define CPU_CLUSTER_CFG_SRST_REQ_CPU3_LEN        1
#define CPU_CLUSTER_CFG_SRST_REQ_CPU3_OFFSET     11
#define CPU_CLUSTER_CFG_SRST_REQ_CPU2_LEN        1
#define CPU_CLUSTER_CFG_SRST_REQ_CPU2_OFFSET     10
#define CPU_CLUSTER_CFG_SRST_REQ_CPU1_LEN        1
#define CPU_CLUSTER_CFG_SRST_REQ_CPU1_OFFSET     9
#define CPU_CLUSTER_CFG_SRST_REQ_CPU0_LEN        1
#define CPU_CLUSTER_CFG_SRST_REQ_CPU0_OFFSET     8
#define CPU_CLUSTER_CFG_SRST_REQ_CPU7_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_REQ_CPU7_POR_OFFSET 7
#define CPU_CLUSTER_CFG_SRST_REQ_CPU6_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_REQ_CPU6_POR_OFFSET 6
#define CPU_CLUSTER_CFG_SRST_REQ_CPU5_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_REQ_CPU5_POR_OFFSET 5
#define CPU_CLUSTER_CFG_SRST_REQ_CPU4_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_REQ_CPU4_POR_OFFSET 4
#define CPU_CLUSTER_CFG_SRST_REQ_CPU3_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_REQ_CPU3_POR_OFFSET 3
#define CPU_CLUSTER_CFG_SRST_REQ_CPU2_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_REQ_CPU2_POR_OFFSET 2
#define CPU_CLUSTER_CFG_SRST_REQ_CPU1_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_REQ_CPU1_POR_OFFSET 1
#define CPU_CLUSTER_CFG_SRST_REQ_CPU0_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_REQ_CPU0_POR_OFFSET 0

#define CPU_CLUSTER_CFG_SRST_DREQ_CPU7_LEN        1
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU7_OFFSET     15
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU6_LEN        1
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU6_OFFSET     14
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU5_LEN        1
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU5_OFFSET     13
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU4_LEN        1
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU4_OFFSET     12
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU3_LEN        1
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU3_OFFSET     11
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU2_LEN        1
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU2_OFFSET     10
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU1_LEN        1
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU1_OFFSET     9
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU0_LEN        1
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU0_OFFSET     8
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU7_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU7_POR_OFFSET 7
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU6_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU6_POR_OFFSET 6
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU5_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU5_POR_OFFSET 5
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU4_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU4_POR_OFFSET 4
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU3_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU3_POR_OFFSET 3
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU2_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU2_POR_OFFSET 2
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU1_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU1_POR_OFFSET 1
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU0_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_DREQ_CPU0_POR_OFFSET 0

#define CPU_CLUSTER_CFG_SRST_REQ_MBIST_LEN    1
#define CPU_CLUSTER_CFG_SRST_REQ_MBIST_OFFSET 0

#define CPU_CLUSTER_CFG_SRST_DREQ_MBIST_LEN    1
#define CPU_CLUSTER_CFG_SRST_DREQ_MBIST_OFFSET 0

#define CPU_CLUSTER_CFG_SRST_REQ_DBG_LEN       1
#define CPU_CLUSTER_CFG_SRST_REQ_DBG_OFFSET    4
#define CPU_CLUSTER_CFG_SRST_REQ_ATB_LEN       1
#define CPU_CLUSTER_CFG_SRST_REQ_ATB_OFFSET    3
#define CPU_CLUSTER_CFG_SRST_REQ_SCU_LEN       1
#define CPU_CLUSTER_CFG_SRST_REQ_SCU_OFFSET    2
#define CPU_CLUSTER_CFG_SRST_REQ_GIC_LEN       1
#define CPU_CLUSTER_CFG_SRST_REQ_GIC_OFFSET    1
#define CPU_CLUSTER_CFG_SRST_REQ_PERIPH_LEN    1
#define CPU_CLUSTER_CFG_SRST_REQ_PERIPH_OFFSET 0

#define CPU_CLUSTER_CFG_SRST_DREQ_DBG_LEN       1
#define CPU_CLUSTER_CFG_SRST_DREQ_DBG_OFFSET    4
#define CPU_CLUSTER_CFG_SRST_DREQ_ATB_LEN       1
#define CPU_CLUSTER_CFG_SRST_DREQ_ATB_OFFSET    3
#define CPU_CLUSTER_CFG_SRST_DREQ_SCU_LEN       1
#define CPU_CLUSTER_CFG_SRST_DREQ_SCU_OFFSET    2
#define CPU_CLUSTER_CFG_SRST_DREQ_GIC_LEN       1
#define CPU_CLUSTER_CFG_SRST_DREQ_GIC_OFFSET    1
#define CPU_CLUSTER_CFG_SRST_DREQ_PERIPH_LEN    1
#define CPU_CLUSTER_CFG_SRST_DREQ_PERIPH_OFFSET 0

#define CPU_CLUSTER_CFG_SRST_REQ_SCU_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_REQ_SCU_POR_OFFSET 0

#define CPU_CLUSTER_CFG_SRST_DREQ_SCU_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_DREQ_SCU_POR_OFFSET 0

#define CPU_CLUSTER_CFG_SRST_REQ_CORE_FSM_LEN    8
#define CPU_CLUSTER_CFG_SRST_REQ_CORE_FSM_OFFSET 1
#define CPU_CLUSTER_CFG_SRST_REQ_FCM_FSM_LEN     1
#define CPU_CLUSTER_CFG_SRST_REQ_FCM_FSM_OFFSET  0

#define CPU_CLUSTER_CFG_SRST_DREQ_CORE_FSM_LEN    1
#define CPU_CLUSTER_CFG_SRST_DREQ_CORE_FSM_OFFSET 1
#define CPU_CLUSTER_CFG_SRST_DREQ_FCM_FSM_LEN     1
#define CPU_CLUSTER_CFG_SRST_DREQ_FCM_FSM_OFFSET  0

#define CPU_CLUSTER_CFG_TSENSOR0_ULTRA_HIGH_LEN    10
#define CPU_CLUSTER_CFG_TSENSOR0_ULTRA_HIGH_OFFSET 20
#define CPU_CLUSTER_CFG_TSENSOR0_HIGH_LEN          10
#define CPU_CLUSTER_CFG_TSENSOR0_HIGH_OFFSET       10
#define CPU_CLUSTER_CFG_TSENSOR0_LOW_LEN           10
#define CPU_CLUSTER_CFG_TSENSOR0_LOW_OFFSET        0

#define CPU_CLUSTER_CFG_TSENSOR0_SAMPLE_SHIFT_NUM_LEN    4
#define CPU_CLUSTER_CFG_TSENSOR0_SAMPLE_SHIFT_NUM_OFFSET 0

#define CPU_CLUSTER_CFG_TSENSOR0_TEMP_CT_SEL_LEN    2
#define CPU_CLUSTER_CFG_TSENSOR0_TEMP_CT_SEL_OFFSET 12
#define CPU_CLUSTER_CFG_TSENSOR0_TEMP_CALIB_LEN     1
#define CPU_CLUSTER_CFG_TSENSOR0_TEMP_CALIB_OFFSET  1
#define CPU_CLUSTER_CFG_TSENSOR0_TEMP_EN_LEN        1
#define CPU_CLUSTER_CFG_TSENSOR0_TEMP_EN_OFFSET     0

#define CPU_CLUSTER_CFG_PMUSNAPSHOTREQ_CLUSTER_LEN    8
#define CPU_CLUSTER_CFG_PMUSNAPSHOTREQ_CLUSTER_OFFSET 0

#define CPU_CLUSTER_CFG_GICCDISABLE_CLUSTER_LEN    1
#define CPU_CLUSTER_CFG_GICCDISABLE_CLUSTER_OFFSET 0

#define CPU_CLUSTER_CFG_BROADCASTCACHEMAINT_CLUSTER_LEN       1
#define CPU_CLUSTER_CFG_BROADCASTCACHEMAINT_CLUSTER_OFFSET    4
#define CPU_CLUSTER_CFG_BROADCASTOUTER_CLUSTER_LEN            1
#define CPU_CLUSTER_CFG_BROADCASTOUTER_CLUSTER_OFFSET         3
#define CPU_CLUSTER_CFG_BROADCASTATOMIC_CLUSTER_LEN           1
#define CPU_CLUSTER_CFG_BROADCASTATOMIC_CLUSTER_OFFSET        2
#define CPU_CLUSTER_CFG_BROADCASTCACHEMAINTPOU_CLUSTER_LEN    1
#define CPU_CLUSTER_CFG_BROADCASTCACHEMAINTPOU_CLUSTER_OFFSET 1
#define CPU_CLUSTER_CFG_BROADCASTPERSIST_CLUSTER_LEN          1
#define CPU_CLUSTER_CFG_BROADCASTPERSIST_CLUSTER_OFFSET       0

#define CPU_CLUSTER_CFG_ICG_EN_CORE_LEN    8
#define CPU_CLUSTER_CFG_ICG_EN_CORE_OFFSET 0

#define CPU_CLUSTER_CFG_SC_CFGEND_LEN    8
#define CPU_CLUSTER_CFG_SC_CFGEND_OFFSET 0

#define CPU_CLUSTER_CFG_SC_VINITHI_LEN    8
#define CPU_CLUSTER_CFG_SC_VINITHI_OFFSET 0

#define CPU_CLUSTER_CFG_RVBARADDR0_CLUSTER_LEN    32
#define CPU_CLUSTER_CFG_RVBARADDR0_CLUSTER_OFFSET 0

#define CPU_CLUSTER_CFG_RVBARADDR1_CLUSTER_LEN    32
#define CPU_CLUSTER_CFG_RVBARADDR1_CLUSTER_OFFSET 0

#define CPU_CLUSTER_CFG_RVBARADDR2_CLUSTER_LEN    32
#define CPU_CLUSTER_CFG_RVBARADDR2_CLUSTER_OFFSET 0

#define CPU_CLUSTER_CFG_RVBARADDR3_CLUSTER_LEN    32
#define CPU_CLUSTER_CFG_RVBARADDR3_CLUSTER_OFFSET 0

#define CPU_CLUSTER_CFG_RVBARADDR4_CLUSTER_LEN    32
#define CPU_CLUSTER_CFG_RVBARADDR4_CLUSTER_OFFSET 0

#define CPU_CLUSTER_CFG_RVBARADDR5_CLUSTER_LEN    32
#define CPU_CLUSTER_CFG_RVBARADDR5_CLUSTER_OFFSET 0

#define CPU_CLUSTER_CFG_RVBARADDR6_CLUSTER_LEN    32
#define CPU_CLUSTER_CFG_RVBARADDR6_CLUSTER_OFFSET 0

#define CPU_CLUSTER_CFG_RVBARADDR7_CLUSTER_LEN    32
#define CPU_CLUSTER_CFG_RVBARADDR7_CLUSTER_OFFSET 0

#define CPU_CLUSTER_CFG_STRETCH_L3RAMCLK_EN_LEN    1
#define CPU_CLUSTER_CFG_STRETCH_L3RAMCLK_EN_OFFSET 0

#define CPU_CLUSTER_CFG_CRYPTODISABLE_CLUSTER_LEN    4
#define CPU_CLUSTER_CFG_CRYPTODISABLE_CLUSTER_OFFSET 0

#define CPU_CLUSTER_CFG_AA64NAA32_LEN    8
#define CPU_CLUSTER_CFG_AA64NAA32_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_SPNIDEN_LEN    1
#define CPU_CLUSTER_CFG_CPU_SPNIDEN_OFFSET 3
#define CPU_CLUSTER_CFG_CPU_SPIDEN_LEN     1
#define CPU_CLUSTER_CFG_CPU_SPIDEN_OFFSET  2
#define CPU_CLUSTER_CFG_CPU_NIDEN_LEN      1
#define CPU_CLUSTER_CFG_CPU_NIDEN_OFFSET   1
#define CPU_CLUSTER_CFG_CPU_DBGEN_LEN      1
#define CPU_CLUSTER_CFG_CPU_DBGEN_OFFSET   0

#define CPU_CLUSTER_CFG_SECURE_DEBUG_EN_CORE7_LEN    1
#define CPU_CLUSTER_CFG_SECURE_DEBUG_EN_CORE7_OFFSET 7
#define CPU_CLUSTER_CFG_SECURE_DEBUG_EN_CORE6_LEN    1
#define CPU_CLUSTER_CFG_SECURE_DEBUG_EN_CORE6_OFFSET 6
#define CPU_CLUSTER_CFG_SECURE_DEBUG_EN_CORE5_LEN    1
#define CPU_CLUSTER_CFG_SECURE_DEBUG_EN_CORE5_OFFSET 5
#define CPU_CLUSTER_CFG_SECURE_DEBUG_EN_CORE4_LEN    1
#define CPU_CLUSTER_CFG_SECURE_DEBUG_EN_CORE4_OFFSET 4
#define CPU_CLUSTER_CFG_SECURE_DEBUG_EN_CORE3_LEN    1
#define CPU_CLUSTER_CFG_SECURE_DEBUG_EN_CORE3_OFFSET 3
#define CPU_CLUSTER_CFG_SECURE_DEBUG_EN_CORE2_LEN    1
#define CPU_CLUSTER_CFG_SECURE_DEBUG_EN_CORE2_OFFSET 2
#define CPU_CLUSTER_CFG_SECURE_DEBUG_EN_CORE1_LEN    1
#define CPU_CLUSTER_CFG_SECURE_DEBUG_EN_CORE1_OFFSET 1
#define CPU_CLUSTER_CFG_SECURE_DEBUG_EN_CORE0_LEN    1
#define CPU_CLUSTER_CFG_SECURE_DEBUG_EN_CORE0_OFFSET 0

#define CPU_CLUSTER_CFG_STRETCH_L2RAMCLK_EN_CORE7_LEN    1
#define CPU_CLUSTER_CFG_STRETCH_L2RAMCLK_EN_CORE7_OFFSET 7
#define CPU_CLUSTER_CFG_STRETCH_L2RAMCLK_EN_CORE6_LEN    1
#define CPU_CLUSTER_CFG_STRETCH_L2RAMCLK_EN_CORE6_OFFSET 6
#define CPU_CLUSTER_CFG_STRETCH_L2RAMCLK_EN_CORE5_LEN    1
#define CPU_CLUSTER_CFG_STRETCH_L2RAMCLK_EN_CORE5_OFFSET 5
#define CPU_CLUSTER_CFG_STRETCH_L2RAMCLK_EN_CORE4_LEN    1
#define CPU_CLUSTER_CFG_STRETCH_L2RAMCLK_EN_CORE4_OFFSET 4
#define CPU_CLUSTER_CFG_STRETCH_L2RAMCLK_EN_CORE3_LEN    1
#define CPU_CLUSTER_CFG_STRETCH_L2RAMCLK_EN_CORE3_OFFSET 3
#define CPU_CLUSTER_CFG_STRETCH_L2RAMCLK_EN_CORE2_LEN    1
#define CPU_CLUSTER_CFG_STRETCH_L2RAMCLK_EN_CORE2_OFFSET 2
#define CPU_CLUSTER_CFG_STRETCH_L2RAMCLK_EN_CORE1_LEN    1
#define CPU_CLUSTER_CFG_STRETCH_L2RAMCLK_EN_CORE1_OFFSET 1
#define CPU_CLUSTER_CFG_STRETCH_L2RAMCLK_EN_CORE0_LEN    1
#define CPU_CLUSTER_CFG_STRETCH_L2RAMCLK_EN_CORE0_OFFSET 0

#define CPU_CLUSTER_CFG_HPM_EN_LEN     1
#define CPU_CLUSTER_CFG_HPM_EN_OFFSET  6
#define CPU_CLUSTER_CFG_HPM_DIV_LEN    6
#define CPU_CLUSTER_CFG_HPM_DIV_OFFSET 0

#define CPU_CLUSTER_CFG_SC_SYSCOACK_LEN    1
#define CPU_CLUSTER_CFG_SC_SYSCOACK_OFFSET 0

#define CPU_CLUSTER_CFG_SMMU_EVENT_MASK_M3_LEN     1
#define CPU_CLUSTER_CFG_SMMU_EVENT_MASK_M3_OFFSET  5
#define CPU_CLUSTER_CFG_SMMU_EVENT_MASK_TS_LEN     1
#define CPU_CLUSTER_CFG_SMMU_EVENT_MASK_TS_OFFSET  4
#define CPU_CLUSTER_CFG_SMMU_EVENT_MASK_A55_LEN    1
#define CPU_CLUSTER_CFG_SMMU_EVENT_MASK_A55_OFFSET 3
#define CPU_CLUSTER_CFG_EVENTI_MASK_TS_LEN         1
#define CPU_CLUSTER_CFG_EVENTI_MASK_TS_OFFSET      2
#define CPU_CLUSTER_CFG_EVENTO_MASK_M3_LEN         1
#define CPU_CLUSTER_CFG_EVENTO_MASK_M3_OFFSET      1
#define CPU_CLUSTER_CFG_EVENTO_MASK_TS_LEN         1
#define CPU_CLUSTER_CFG_EVENTO_MASK_TS_OFFSET      0

#define CPU_CLUSTER_CFG_CPU_CORE_BTAC0_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_CORE_BTAC0_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_CORE_BTAC1_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_CORE_BTAC1_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_CORE_DDATA_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_CORE_DDATA_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_CORE_DDIRTY_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_CORE_DDIRTY_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_CORE_DTAG_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_CORE_DTAG_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_CORE_IDATA_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_CORE_IDATA_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_CORE_ITAG_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_CORE_ITAG_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_L2_DATA_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_L2_DATA_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_L2_DB_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_L2_DB_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_L2_TAG_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_L2_TAG_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_L2_VICTIM_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_L2_VICTIM_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_TLB_DATA_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_TLB_DATA_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_TLB_TAG_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_TLB_TAG_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_L3_DATA_WAY3_0_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_L3_DATA_WAY3_0_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_L3_DATA_WAY7_4_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_L3_DATA_WAY7_4_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_L3_DATA_WAY11_8_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_L3_DATA_WAY11_8_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_L3_DATA_WAY15_12_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_L3_DATA_WAY15_12_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_L3_TAG_WAY3_0_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_L3_TAG_WAY3_0_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_L3_TAG_WAY7_4_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_L3_TAG_WAY7_4_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_L3_TAG_WAY11_8_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_L3_TAG_WAY11_8_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_L3_TAG_WAY15_12_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_L3_TAG_WAY15_12_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_L3_VICITIM_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_L3_VICITIM_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_SCU_LTDB_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_SCU_LTDB_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_SCU_SF_MEM_CTRL_LEN    32
#define CPU_CLUSTER_CFG_CPU_SCU_SF_MEM_CTRL_OFFSET 0

#define CPU_CLUSTER_CFG_SC_SP_RAM_TMOD_ULTRASOC_LEN    4
#define CPU_CLUSTER_CFG_SC_SP_RAM_TMOD_ULTRASOC_OFFSET 0

#define CPU_CLUSTER_CFG_SC_CFGTE_LEN    8
#define CPU_CLUSTER_CFG_SC_CFGTE_OFFSET 0

#define CPU_CLUSTER_CFG_TSENSOR0_ULTRA_OVER_LEN    1
#define CPU_CLUSTER_CFG_TSENSOR0_ULTRA_OVER_OFFSET 2
#define CPU_CLUSTER_CFG_TSENSOR0_OVER_LEN          1
#define CPU_CLUSTER_CFG_TSENSOR0_OVER_OFFSET       1
#define CPU_CLUSTER_CFG_TSENSOR0_UNDER_LEN         1
#define CPU_CLUSTER_CFG_TSENSOR0_UNDER_OFFSET      0

#define CPU_CLUSTER_CFG_TSENSOR0_ULTRA_OVER_INT_MASK_LEN    1
#define CPU_CLUSTER_CFG_TSENSOR0_ULTRA_OVER_INT_MASK_OFFSET 2
#define CPU_CLUSTER_CFG_TSENSOR0_OVER_INT_MASK_LEN          1
#define CPU_CLUSTER_CFG_TSENSOR0_OVER_INT_MASK_OFFSET       1
#define CPU_CLUSTER_CFG_TSENSOR0_UNDER_INT_MASK_LEN         1
#define CPU_CLUSTER_CFG_TSENSOR0_UNDER_INT_MASK_OFFSET      0

#define CPU_CLUSTER_CFG_ICG_ST_DBG_LEN       1
#define CPU_CLUSTER_CFG_ICG_ST_DBG_OFFSET    4
#define CPU_CLUSTER_CFG_ICG_ST_ATB_LEN       1
#define CPU_CLUSTER_CFG_ICG_ST_ATB_OFFSET    3
#define CPU_CLUSTER_CFG_ICG_ST_GIC_LEN       1
#define CPU_CLUSTER_CFG_ICG_ST_GIC_OFFSET    2
#define CPU_CLUSTER_CFG_ICG_ST_SCU_LEN       1
#define CPU_CLUSTER_CFG_ICG_ST_SCU_OFFSET    1
#define CPU_CLUSTER_CFG_ICG_ST_PERIPH_LEN    1
#define CPU_CLUSTER_CFG_ICG_ST_PERIPH_OFFSET 0

#define CPU_CLUSTER_CFG_ICG_ST_MBIST_CORE_LEN       1
#define CPU_CLUSTER_CFG_ICG_ST_MBIST_CORE_OFFSET    1
#define CPU_CLUSTER_CFG_ICG_ST_MBIST_FCM_PPU_LEN    1
#define CPU_CLUSTER_CFG_ICG_ST_MBIST_FCM_PPU_OFFSET 0

#define CPU_CLUSTER_CFG_SRST_ST_CPU7_LEN        1
#define CPU_CLUSTER_CFG_SRST_ST_CPU7_OFFSET     15
#define CPU_CLUSTER_CFG_SRST_ST_CPU6_LEN        1
#define CPU_CLUSTER_CFG_SRST_ST_CPU6_OFFSET     14
#define CPU_CLUSTER_CFG_SRST_ST_CPU5_LEN        1
#define CPU_CLUSTER_CFG_SRST_ST_CPU5_OFFSET     13
#define CPU_CLUSTER_CFG_SRST_ST_CPU4_LEN        1
#define CPU_CLUSTER_CFG_SRST_ST_CPU4_OFFSET     12
#define CPU_CLUSTER_CFG_SRST_ST_CPU3_LEN        1
#define CPU_CLUSTER_CFG_SRST_ST_CPU3_OFFSET     11
#define CPU_CLUSTER_CFG_SRST_ST_CPU2_LEN        1
#define CPU_CLUSTER_CFG_SRST_ST_CPU2_OFFSET     10
#define CPU_CLUSTER_CFG_SRST_ST_CPU1_LEN        1
#define CPU_CLUSTER_CFG_SRST_ST_CPU1_OFFSET     9
#define CPU_CLUSTER_CFG_SRST_ST_CPU0_LEN        1
#define CPU_CLUSTER_CFG_SRST_ST_CPU0_OFFSET     8
#define CPU_CLUSTER_CFG_SRST_ST_CPU7_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_ST_CPU7_POR_OFFSET 7
#define CPU_CLUSTER_CFG_SRST_ST_CPU6_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_ST_CPU6_POR_OFFSET 6
#define CPU_CLUSTER_CFG_SRST_ST_CPU5_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_ST_CPU5_POR_OFFSET 5
#define CPU_CLUSTER_CFG_SRST_ST_CPU4_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_ST_CPU4_POR_OFFSET 4
#define CPU_CLUSTER_CFG_SRST_ST_CPU3_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_ST_CPU3_POR_OFFSET 3
#define CPU_CLUSTER_CFG_SRST_ST_CPU2_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_ST_CPU2_POR_OFFSET 2
#define CPU_CLUSTER_CFG_SRST_ST_CPU1_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_ST_CPU1_POR_OFFSET 1
#define CPU_CLUSTER_CFG_SRST_ST_CPU0_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_ST_CPU0_POR_OFFSET 0

#define CPU_CLUSTER_CFG_SRST_ST_MBIST_LEN    1
#define CPU_CLUSTER_CFG_SRST_ST_MBIST_OFFSET 0

#define CPU_CLUSTER_CFG_SRST_ST_DBG_LEN       1
#define CPU_CLUSTER_CFG_SRST_ST_DBG_OFFSET    4
#define CPU_CLUSTER_CFG_SRST_ST_ATB_LEN       1
#define CPU_CLUSTER_CFG_SRST_ST_ATB_OFFSET    3
#define CPU_CLUSTER_CFG_SRST_ST_SCU_LEN       1
#define CPU_CLUSTER_CFG_SRST_ST_SCU_OFFSET    2
#define CPU_CLUSTER_CFG_SRST_ST_GIC_LEN       1
#define CPU_CLUSTER_CFG_SRST_ST_GIC_OFFSET    1
#define CPU_CLUSTER_CFG_SRST_ST_PERIPH_LEN    1
#define CPU_CLUSTER_CFG_SRST_ST_PERIPH_OFFSET 0

#define CPU_CLUSTER_CFG_SRST_ST_SCU_POR_LEN    1
#define CPU_CLUSTER_CFG_SRST_ST_SCU_POR_OFFSET 0

#define CPU_CLUSTER_CFG_SRST_ST_CORE_FSM_LEN    8
#define CPU_CLUSTER_CFG_SRST_ST_CORE_FSM_OFFSET 1
#define CPU_CLUSTER_CFG_SRST_ST_FCM_FSM_LEN     1
#define CPU_CLUSTER_CFG_SRST_ST_FCM_FSM_OFFSET  0

#define CPU_CLUSTER_CFG_TSENSOR0_TEMP_READY_LEN    1
#define CPU_CLUSTER_CFG_TSENSOR0_TEMP_READY_OFFSET 12
#define CPU_CLUSTER_CFG_TSENSOR0_TEMP_OUT_LEN      10
#define CPU_CLUSTER_CFG_TSENSOR0_TEMP_OUT_OFFSET   0

#define CPU_CLUSTER_CFG_TSENSOR0_VALID_LEN     1
#define CPU_CLUSTER_CFG_TSENSOR0_VALID_OFFSET  31
#define CPU_CLUSTER_CFG_TSENSOR0_SAMPLE_LEN    10
#define CPU_CLUSTER_CFG_TSENSOR0_SAMPLE_OFFSET 0

#define CPU_CLUSTER_CFG_PMUSNAPSHOTACK_CLUSTER_LEN    4
#define CPU_CLUSTER_CFG_PMUSNAPSHOTACK_CLUSTER_OFFSET 0

#define CPU_CLUSTER_CFG_STANDBYWFE_CLUSTER_LEN    8
#define CPU_CLUSTER_CFG_STANDBYWFE_CLUSTER_OFFSET 0

#define CPU_CLUSTER_CFG_STANDBYWFI_CLUSTER_LEN    8
#define CPU_CLUSTER_CFG_STANDBYWFI_CLUSTER_OFFSET 0

#define CPU_CLUSTER_CFG_SC_COREINSTRRET_LEN    8
#define CPU_CLUSTER_CFG_SC_COREINSTRRET_OFFSET 0

#define CPU_CLUSTER_CFG_SC_COREINSTRRUN_LEN    8
#define CPU_CLUSTER_CFG_SC_COREINSTRRUN_OFFSET 0

#define CPU_CLUSTER_CFG_ECO_PM_CCNT_Q_63BIT_CORE0_LEN    1
#define CPU_CLUSTER_CFG_ECO_PM_CCNT_Q_63BIT_CORE0_OFFSET 3
#define CPU_CLUSTER_CFG_GIC_IRQ_CORE0_LEN                1
#define CPU_CLUSTER_CFG_GIC_IRQ_CORE0_OFFSET             2
#define CPU_CLUSTER_CFG_GIC_FIQ_CORE0_LEN                1
#define CPU_CLUSTER_CFG_GIC_FIQ_CORE0_OFFSET             1
#define CPU_CLUSTER_CFG_DBGACK_CORE0_LEN                 1
#define CPU_CLUSTER_CFG_DBGACK_CORE0_OFFSET              0

#define CPU_CLUSTER_CFG_ECO_PM_CCNT_Q_63BIT_CORE1_LEN    1
#define CPU_CLUSTER_CFG_ECO_PM_CCNT_Q_63BIT_CORE1_OFFSET 3
#define CPU_CLUSTER_CFG_GIC_IRQ_CORE1_LEN                1
#define CPU_CLUSTER_CFG_GIC_IRQ_CORE1_OFFSET             2
#define CPU_CLUSTER_CFG_GIC_FIQ_CORE1_LEN                1
#define CPU_CLUSTER_CFG_GIC_FIQ_CORE1_OFFSET             1
#define CPU_CLUSTER_CFG_DBGACK_CORE1_LEN                 1
#define CPU_CLUSTER_CFG_DBGACK_CORE1_OFFSET              0

#define CPU_CLUSTER_CFG_ECO_PM_CCNT_Q_63BIT_CORE2_LEN    1
#define CPU_CLUSTER_CFG_ECO_PM_CCNT_Q_63BIT_CORE2_OFFSET 3
#define CPU_CLUSTER_CFG_GIC_IRQ_CORE2_LEN                1
#define CPU_CLUSTER_CFG_GIC_IRQ_CORE2_OFFSET             2
#define CPU_CLUSTER_CFG_GIC_FIQ_CORE2_LEN                1
#define CPU_CLUSTER_CFG_GIC_FIQ_CORE2_OFFSET             1
#define CPU_CLUSTER_CFG_DBGACK_CORE2_LEN                 1
#define CPU_CLUSTER_CFG_DBGACK_CORE2_OFFSET              0

#define CPU_CLUSTER_CFG_ECO_PM_CCNT_Q_63BIT_CORE3_LEN    1
#define CPU_CLUSTER_CFG_ECO_PM_CCNT_Q_63BIT_CORE3_OFFSET 3
#define CPU_CLUSTER_CFG_GIC_IRQ_CORE3_LEN                1
#define CPU_CLUSTER_CFG_GIC_IRQ_CORE3_OFFSET             2
#define CPU_CLUSTER_CFG_GIC_FIQ_CORE3_LEN                1
#define CPU_CLUSTER_CFG_GIC_FIQ_CORE3_OFFSET             1
#define CPU_CLUSTER_CFG_DBGACK_CORE3_LEN                 1
#define CPU_CLUSTER_CFG_DBGACK_CORE3_OFFSET              0

#define CPU_CLUSTER_CFG_ECO_PM_CCNT_Q_63BIT_CORE4_LEN    1
#define CPU_CLUSTER_CFG_ECO_PM_CCNT_Q_63BIT_CORE4_OFFSET 3
#define CPU_CLUSTER_CFG_GIC_IRQ_CORE4_LEN                1
#define CPU_CLUSTER_CFG_GIC_IRQ_CORE4_OFFSET             2
#define CPU_CLUSTER_CFG_GIC_FIQ_CORE4_LEN                1
#define CPU_CLUSTER_CFG_GIC_FIQ_CORE4_OFFSET             1
#define CPU_CLUSTER_CFG_DBGACK_CORE4_LEN                 1
#define CPU_CLUSTER_CFG_DBGACK_CORE4_OFFSET              0

#define CPU_CLUSTER_CFG_ECO_PM_CCNT_Q_63BIT_CORE5_LEN    1
#define CPU_CLUSTER_CFG_ECO_PM_CCNT_Q_63BIT_CORE5_OFFSET 3
#define CPU_CLUSTER_CFG_GIC_IRQ_CORE5_LEN                1
#define CPU_CLUSTER_CFG_GIC_IRQ_CORE5_OFFSET             2
#define CPU_CLUSTER_CFG_GIC_FIQ_CORE5_LEN                1
#define CPU_CLUSTER_CFG_GIC_FIQ_CORE5_OFFSET             1
#define CPU_CLUSTER_CFG_DBGACK_CORE5_LEN                 1
#define CPU_CLUSTER_CFG_DBGACK_CORE5_OFFSET              0

#define CPU_CLUSTER_CFG_ECO_PM_CCNT_Q_63BIT_CORE6_LEN    1
#define CPU_CLUSTER_CFG_ECO_PM_CCNT_Q_63BIT_CORE6_OFFSET 3
#define CPU_CLUSTER_CFG_GIC_IRQ_CORE6_LEN                1
#define CPU_CLUSTER_CFG_GIC_IRQ_CORE6_OFFSET             2
#define CPU_CLUSTER_CFG_GIC_FIQ_CORE6_LEN                1
#define CPU_CLUSTER_CFG_GIC_FIQ_CORE6_OFFSET             1
#define CPU_CLUSTER_CFG_DBGACK_CORE6_LEN                 1
#define CPU_CLUSTER_CFG_DBGACK_CORE6_OFFSET              0

#define CPU_CLUSTER_CFG_ECO_PM_CCNT_Q_63BIT_CORE7_LEN    1
#define CPU_CLUSTER_CFG_ECO_PM_CCNT_Q_63BIT_CORE7_OFFSET 3
#define CPU_CLUSTER_CFG_GIC_IRQ_CORE7_LEN                1
#define CPU_CLUSTER_CFG_GIC_IRQ_CORE7_OFFSET             2
#define CPU_CLUSTER_CFG_GIC_FIQ_CORE7_LEN                1
#define CPU_CLUSTER_CFG_GIC_FIQ_CORE7_OFFSET             1
#define CPU_CLUSTER_CFG_DBGACK_CORE7_LEN                 1
#define CPU_CLUSTER_CFG_DBGACK_CORE7_OFFSET              0

#define CPU_CLUSTER_CFG_TSENSOR0_ULTRA_OVER_INT_STATUS_LEN    1
#define CPU_CLUSTER_CFG_TSENSOR0_ULTRA_OVER_INT_STATUS_OFFSET 2
#define CPU_CLUSTER_CFG_TSENSOR0_OVER_INT_STATUS_LEN          1
#define CPU_CLUSTER_CFG_TSENSOR0_OVER_INT_STATUS_OFFSET       1
#define CPU_CLUSTER_CFG_TSENSOR0_UNDER_INT_STATUS_LEN         1
#define CPU_CLUSTER_CFG_TSENSOR0_UNDER_INT_STATUS_OFFSET      0

#define CPU_CLUSTER_CFG_HPM_PC_1_ORG_LEN    10
#define CPU_CLUSTER_CFG_HPM_PC_1_ORG_OFFSET 15
#define CPU_CLUSTER_CFG_HPM_PC_0_ORG_LEN    10
#define CPU_CLUSTER_CFG_HPM_PC_0_ORG_OFFSET 3
#define CPU_CLUSTER_CFG_HPM_PC_VALID_LEN    1
#define CPU_CLUSTER_CFG_HPM_PC_VALID_OFFSET 0

#define CPU_CLUSTER_CFG_SC_SYSCOREQ_LEN    1
#define CPU_CLUSTER_CFG_SC_SYSCOREQ_OFFSET 0

#define CPU_CLUSTER_CFG_SC_REG_CLUSTERPMCCNTR_63BIT_LEN    1
#define CPU_CLUSTER_CFG_SC_REG_CLUSTERPMCCNTR_63BIT_OFFSET 8
#define CPU_CLUSTER_CFG_SC_PWRUPCPU_ACK_LEN                8
#define CPU_CLUSTER_CFG_SC_PWRUPCPU_ACK_OFFSET             0

#define CPU_CLUSTER_CFG_DBGNOPWRDWN_PATCH_LEN    1
#define CPU_CLUSTER_CFG_DBGNOPWRDWN_PATCH_OFFSET 0

#define CPU_CLUSTER_CFG_A55_WFI_BYPASS_LEN    1
#define CPU_CLUSTER_CFG_A55_WFI_BYPASS_OFFSET 3
#define CPU_CLUSTER_CFG_A55_WFE_BYPASS_LEN    1
#define CPU_CLUSTER_CFG_A55_WFE_BYPASS_OFFSET 2
#define CPU_CLUSTER_CFG_A55_PDN_BYPASS_LEN    1
#define CPU_CLUSTER_CFG_A55_PDN_BYPASS_OFFSET 1
#define CPU_CLUSTER_CFG_WFI_SOURCE_SEL_LEN    1
#define CPU_CLUSTER_CFG_WFI_SOURCE_SEL_OFFSET 0

#define CPU_CLUSTER_CFG_FCM_P_CHANNEL_ENABLE_LEN                1
#define CPU_CLUSTER_CFG_FCM_P_CHANNEL_ENABLE_OFFSET             31
#define CPU_CLUSTER_CFG_CLUSTER_PACTIVE_SEL_LEN                 1
#define CPU_CLUSTER_CFG_CLUSTER_PACTIVE_SEL_OFFSET              24
#define CPU_CLUSTER_CFG_CLUSTER_PSTATE_FROM_SYS_LEN             7
#define CPU_CLUSTER_CFG_CLUSTER_PSTATE_FROM_SYS_OFFSET          16
#define CPU_CLUSTER_CFG_CLUSTER_PREQ_FROM_SYS_LEN               1
#define CPU_CLUSTER_CFG_CLUSTER_PREQ_FROM_SYS_OFFSET            15
#define CPU_CLUSTER_CFG_FORCE_OFF_TO_ON_LEN                     1
#define CPU_CLUSTER_CFG_FORCE_OFF_TO_ON_OFFSET                  12
#define CPU_CLUSTER_CFG_FORCE_FLUSH_CACHE_LEN                   1
#define CPU_CLUSTER_CFG_FORCE_FLUSH_CACHE_OFFSET                11
#define CPU_CLUSTER_CFG_FORCE_DISABLE_OFF_LEN                   1
#define CPU_CLUSTER_CFG_FORCE_DISABLE_OFF_OFFSET                10
#define CPU_CLUSTER_CFG_FORCED_ON_TO_SFONLY_TO_ON_LEN           1
#define CPU_CLUSTER_CFG_FORCED_ON_TO_SFONLY_TO_ON_OFFSET        9
#define CPU_CLUSTER_CFG_FORCED_ON_TO_SFONLY_TO_ON_ENABLE_LEN    1
#define CPU_CLUSTER_CFG_FORCED_ON_TO_SFONLY_TO_ON_ENABLE_OFFSET 8
#define CPU_CLUSTER_CFG_FCM_P_CHANNEL_INIT_PSTATE_LEN           7
#define CPU_CLUSTER_CFG_FCM_P_CHANNEL_INIT_PSTATE_OFFSET        0

#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_L3_TAG_WAY3_WAY0_FROM_SYS_LEN       3
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_L3_TAG_WAY3_WAY0_FROM_SYS_OFFSET    29
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_L3_TAG_WAY7_WAY4_FROM_SYS_LEN       3
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_L3_TAG_WAY7_WAY4_FROM_SYS_OFFSET    26
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_L3_TAG_WAY11_WAY8_FROM_SYS_LEN      3
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_L3_TAG_WAY11_WAY8_FROM_SYS_OFFSET   23
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_L3_TAG_WAY15_WAY12_FROM_SYS_LEN     3
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_L3_TAG_WAY15_WAY12_FROM_SYS_OFFSET  20
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_OTHERS_FROM_SYS_LEN                 3
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_OTHERS_FROM_SYS_OFFSET              15
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_SFONLY_FROM_SYS_LEN                 3
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_SFONLY_FROM_SYS_OFFSET              12
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_L3_DATA_WAY3_WAY0_FROM_SYS_LEN      3
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_L3_DATA_WAY3_WAY0_FROM_SYS_OFFSET   9
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_L3_DATA_WAY7_WAY4_FROM_SYS_LEN      3
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_L3_DATA_WAY7_WAY4_FROM_SYS_OFFSET   6
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_L3_DATA_WAY11_WAY8_FROM_SYS_LEN     3
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_L3_DATA_WAY11_WAY8_FROM_SYS_OFFSET  3
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_L3_DATA_WAY15_WAY12_FROM_SYS_LEN    3
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_L3_DATA_WAY15_WAY12_FROM_SYS_OFFSET 0

#define CPU_CLUSTER_CFG_CLUSTER_MEM_SCU_FROM_SYS_LEN    16
#define CPU_CLUSTER_CFG_CLUSTER_MEM_SCU_FROM_SYS_OFFSET 0

#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_L3D_FROM_SYS_LEN    16
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_L3D_FROM_SYS_OFFSET 16
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_L3T_FROM_SYS_LEN    16
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_L3T_FROM_SYS_OFFSET 0

#define CPU_CLUSTER_CFG_CORE0_P_CHANNEL_ENABLE_LEN            1
#define CPU_CLUSTER_CFG_CORE0_P_CHANNEL_ENABLE_OFFSET         31
#define CPU_CLUSTER_CFG_CORE0_MEM_CTRL_FROM_SYS_LEN           3
#define CPU_CLUSTER_CFG_CORE0_MEM_CTRL_FROM_SYS_OFFSET        28
#define CPU_CLUSTER_CFG_CORE0_PREQ_FROM_SYS_LEN               1
#define CPU_CLUSTER_CFG_CORE0_PREQ_FROM_SYS_OFFSET            24
#define CPU_CLUSTER_CFG_CORE0_PSTATE_FROM_SYS_LEN             6
#define CPU_CLUSTER_CFG_CORE0_PSTATE_FROM_SYS_OFFSET          16
#define CPU_CLUSTER_CFG_CORE0_P_CHANNEL_INITIAL_PSTATE_LEN    6
#define CPU_CLUSTER_CFG_CORE0_P_CHANNEL_INITIAL_PSTATE_OFFSET 0

#define CPU_CLUSTER_CFG_CORE1_P_CHANNEL_ENABLE_LEN            1
#define CPU_CLUSTER_CFG_CORE1_P_CHANNEL_ENABLE_OFFSET         31
#define CPU_CLUSTER_CFG_CORE1_MEM_CTRL_FROM_SYS_LEN           3
#define CPU_CLUSTER_CFG_CORE1_MEM_CTRL_FROM_SYS_OFFSET        28
#define CPU_CLUSTER_CFG_CORE1_PREQ_FROM_SYS_LEN               1
#define CPU_CLUSTER_CFG_CORE1_PREQ_FROM_SYS_OFFSET            24
#define CPU_CLUSTER_CFG_CORE1_PSTATE_FROM_SYS_LEN             6
#define CPU_CLUSTER_CFG_CORE1_PSTATE_FROM_SYS_OFFSET          16
#define CPU_CLUSTER_CFG_CORE1_P_CHANNEL_INITIAL_PSTATE_LEN    6
#define CPU_CLUSTER_CFG_CORE1_P_CHANNEL_INITIAL_PSTATE_OFFSET 0

#define CPU_CLUSTER_CFG_CORE2_P_CHANNEL_ENABLE_LEN            1
#define CPU_CLUSTER_CFG_CORE2_P_CHANNEL_ENABLE_OFFSET         31
#define CPU_CLUSTER_CFG_CORE2_MEM_CTRL_FROM_SYS_LEN           3
#define CPU_CLUSTER_CFG_CORE2_MEM_CTRL_FROM_SYS_OFFSET        28
#define CPU_CLUSTER_CFG_CORE2_PREQ_FROM_SYS_LEN               1
#define CPU_CLUSTER_CFG_CORE2_PREQ_FROM_SYS_OFFSET            24
#define CPU_CLUSTER_CFG_CORE2_PSTATE_FROM_SYS_LEN             6
#define CPU_CLUSTER_CFG_CORE2_PSTATE_FROM_SYS_OFFSET          16
#define CPU_CLUSTER_CFG_CORE2_P_CHANNEL_INITIAL_PSTATE_LEN    6
#define CPU_CLUSTER_CFG_CORE2_P_CHANNEL_INITIAL_PSTATE_OFFSET 0

#define CPU_CLUSTER_CFG_CORE3_P_CHANNEL_ENABLE_LEN            1
#define CPU_CLUSTER_CFG_CORE3_P_CHANNEL_ENABLE_OFFSET         31
#define CPU_CLUSTER_CFG_CORE3_MEM_CTRL_FROM_SYS_LEN           3
#define CPU_CLUSTER_CFG_CORE3_MEM_CTRL_FROM_SYS_OFFSET        28
#define CPU_CLUSTER_CFG_CORE3_PREQ_FROM_SYS_LEN               1
#define CPU_CLUSTER_CFG_CORE3_PREQ_FROM_SYS_OFFSET            24
#define CPU_CLUSTER_CFG_CORE3_PSTATE_FROM_SYS_LEN             6
#define CPU_CLUSTER_CFG_CORE3_PSTATE_FROM_SYS_OFFSET          16
#define CPU_CLUSTER_CFG_CORE3_P_CHANNEL_INITIAL_PSTATE_LEN    6
#define CPU_CLUSTER_CFG_CORE3_P_CHANNEL_INITIAL_PSTATE_OFFSET 0

#define CPU_CLUSTER_CFG_CORE4_P_CHANNEL_ENABLE_LEN            1
#define CPU_CLUSTER_CFG_CORE4_P_CHANNEL_ENABLE_OFFSET         31
#define CPU_CLUSTER_CFG_CORE4_MEM_CTRL_FROM_SYS_LEN           3
#define CPU_CLUSTER_CFG_CORE4_MEM_CTRL_FROM_SYS_OFFSET        28
#define CPU_CLUSTER_CFG_CORE4_PREQ_FROM_SYS_LEN               1
#define CPU_CLUSTER_CFG_CORE4_PREQ_FROM_SYS_OFFSET            24
#define CPU_CLUSTER_CFG_CORE4_PSTATE_FROM_SYS_LEN             6
#define CPU_CLUSTER_CFG_CORE4_PSTATE_FROM_SYS_OFFSET          16
#define CPU_CLUSTER_CFG_CORE4_P_CHANNEL_INITIAL_PSTATE_LEN    6
#define CPU_CLUSTER_CFG_CORE4_P_CHANNEL_INITIAL_PSTATE_OFFSET 0

#define CPU_CLUSTER_CFG_CORE5_P_CHANNEL_ENABLE_LEN            1
#define CPU_CLUSTER_CFG_CORE5_P_CHANNEL_ENABLE_OFFSET         31
#define CPU_CLUSTER_CFG_CORE5_MEM_CTRL_FROM_SYS_LEN           3
#define CPU_CLUSTER_CFG_CORE5_MEM_CTRL_FROM_SYS_OFFSET        28
#define CPU_CLUSTER_CFG_CORE5_PREQ_FROM_SYS_LEN               1
#define CPU_CLUSTER_CFG_CORE5_PREQ_FROM_SYS_OFFSET            24
#define CPU_CLUSTER_CFG_CORE5_PSTATE_FROM_SYS_LEN             6
#define CPU_CLUSTER_CFG_CORE5_PSTATE_FROM_SYS_OFFSET          16
#define CPU_CLUSTER_CFG_CORE5_P_CHANNEL_INITIAL_PSTATE_LEN    6
#define CPU_CLUSTER_CFG_CORE5_P_CHANNEL_INITIAL_PSTATE_OFFSET 0

#define CPU_CLUSTER_CFG_CORE6_P_CHANNEL_ENABLE_LEN            1
#define CPU_CLUSTER_CFG_CORE6_P_CHANNEL_ENABLE_OFFSET         31
#define CPU_CLUSTER_CFG_CORE6_MEM_CTRL_FROM_SYS_LEN           3
#define CPU_CLUSTER_CFG_CORE6_MEM_CTRL_FROM_SYS_OFFSET        28
#define CPU_CLUSTER_CFG_CORE6_PREQ_FROM_SYS_LEN               1
#define CPU_CLUSTER_CFG_CORE6_PREQ_FROM_SYS_OFFSET            24
#define CPU_CLUSTER_CFG_CORE6_PSTATE_FROM_SYS_LEN             6
#define CPU_CLUSTER_CFG_CORE6_PSTATE_FROM_SYS_OFFSET          16
#define CPU_CLUSTER_CFG_CORE6_P_CHANNEL_INITIAL_PSTATE_LEN    6
#define CPU_CLUSTER_CFG_CORE6_P_CHANNEL_INITIAL_PSTATE_OFFSET 0

#define CPU_CLUSTER_CFG_CORE7_P_CHANNEL_ENABLE_LEN            1
#define CPU_CLUSTER_CFG_CORE7_P_CHANNEL_ENABLE_OFFSET         31
#define CPU_CLUSTER_CFG_CORE7_MEM_CTRL_FROM_SYS_LEN           3
#define CPU_CLUSTER_CFG_CORE7_MEM_CTRL_FROM_SYS_OFFSET        28
#define CPU_CLUSTER_CFG_CORE7_PREQ_FROM_SYS_LEN               1
#define CPU_CLUSTER_CFG_CORE7_PREQ_FROM_SYS_OFFSET            24
#define CPU_CLUSTER_CFG_CORE7_PSTATE_FROM_SYS_LEN             6
#define CPU_CLUSTER_CFG_CORE7_PSTATE_FROM_SYS_OFFSET          16
#define CPU_CLUSTER_CFG_CORE7_P_CHANNEL_INITIAL_PSTATE_LEN    6
#define CPU_CLUSTER_CFG_CORE7_P_CHANNEL_INITIAL_PSTATE_OFFSET 0

#define CPU_CLUSTER_CFG_ANANKE_CORE_MEM_CTRL_SLP_LEN       3
#define CPU_CLUSTER_CFG_ANANKE_CORE_MEM_CTRL_SLP_OFFSET    12
#define CPU_CLUSTER_CFG_ANANKE_CORE_MEM_CTRL_DSLP_LEN      3
#define CPU_CLUSTER_CFG_ANANKE_CORE_MEM_CTRL_DSLP_OFFSET   8
#define CPU_CLUSTER_CFG_ANANKE_CORE_MEM_CTRL_SD_LEN        3
#define CPU_CLUSTER_CFG_ANANKE_CORE_MEM_CTRL_SD_OFFSET     4
#define CPU_CLUSTER_CFG_ANANKE_CORE_MEM_CTRL_NORMAL_LEN    3
#define CPU_CLUSTER_CFG_ANANKE_CORE_MEM_CTRL_NORMAL_OFFSET 0

#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_SLP_LEN       3
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_SLP_OFFSET    12
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_DSLP_LEN      3
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_DSLP_OFFSET   8
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_SD_LEN        3
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_SD_OFFSET     4
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_NORMAL_LEN    3
#define CPU_CLUSTER_CFG_CLUSTER_MEM_CTRL_NORMAL_OFFSET 0

#define CPU_CLUSTER_CFG_GICCLK_Q_CHANNEL_ENABLE_LEN    1
#define CPU_CLUSTER_CFG_GICCLK_Q_CHANNEL_ENABLE_OFFSET 3
#define CPU_CLUSTER_CFG_PCLK_Q_CHANNEL_ENABLE_LEN      1
#define CPU_CLUSTER_CFG_PCLK_Q_CHANNEL_ENABLE_OFFSET   2
#define CPU_CLUSTER_CFG_ATCLK_Q_CHANNEL_ENABLE_LEN     1
#define CPU_CLUSTER_CFG_ATCLK_Q_CHANNEL_ENABLE_OFFSET  1
#define CPU_CLUSTER_CFG_SCLK_Q_CHANNEL_ENABLE_LEN      1
#define CPU_CLUSTER_CFG_SCLK_Q_CHANNEL_ENABLE_OFFSET   0

#define CPU_CLUSTER_CFG_GICCLK_Q_CHANNEL_CFGCNT_LEN    7
#define CPU_CLUSTER_CFG_GICCLK_Q_CHANNEL_CFGCNT_OFFSET 24
#define CPU_CLUSTER_CFG_PCLK_Q_CHANNEL_CFGCNT_LEN      7
#define CPU_CLUSTER_CFG_PCLK_Q_CHANNEL_CFGCNT_OFFSET   16
#define CPU_CLUSTER_CFG_ATCLK_Q_CHANNEL_CFGCNT_LEN     7
#define CPU_CLUSTER_CFG_ATCLK_Q_CHANNEL_CFGCNT_OFFSET  8
#define CPU_CLUSTER_CFG_SCLK_Q_CHANNEL_CFGCNT_LEN      7
#define CPU_CLUSTER_CFG_SCLK_Q_CHANNEL_CFGCNT_OFFSET   0

#define CPU_CLUSTER_CFG_CORE0_P_CHANNEL_WAIT_CYCLE_LEN    16
#define CPU_CLUSTER_CFG_CORE0_P_CHANNEL_WAIT_CYCLE_OFFSET 16
#define CPU_CLUSTER_CFG_CORE1_P_CHANNEL_WAIT_CYCLE_LEN    16
#define CPU_CLUSTER_CFG_CORE1_P_CHANNEL_WAIT_CYCLE_OFFSET 0

#define CPU_CLUSTER_CFG_CORE2_P_CHANNEL_WAIT_CYCLE_LEN    16
#define CPU_CLUSTER_CFG_CORE2_P_CHANNEL_WAIT_CYCLE_OFFSET 16
#define CPU_CLUSTER_CFG_CORE3_P_CHANNEL_WAIT_CYCLE_LEN    16
#define CPU_CLUSTER_CFG_CORE3_P_CHANNEL_WAIT_CYCLE_OFFSET 0

#define CPU_CLUSTER_CFG_CORE4_P_CHANNEL_WAIT_CYCLE_LEN    16
#define CPU_CLUSTER_CFG_CORE4_P_CHANNEL_WAIT_CYCLE_OFFSET 16
#define CPU_CLUSTER_CFG_CORE5_P_CHANNEL_WAIT_CYCLE_LEN    16
#define CPU_CLUSTER_CFG_CORE5_P_CHANNEL_WAIT_CYCLE_OFFSET 0

#define CPU_CLUSTER_CFG_CORE6_P_CHANNEL_WAIT_CYCLE_LEN    16
#define CPU_CLUSTER_CFG_CORE6_P_CHANNEL_WAIT_CYCLE_OFFSET 16
#define CPU_CLUSTER_CFG_CORE7_P_CHANNEL_WAIT_CYCLE_LEN    16
#define CPU_CLUSTER_CFG_CORE7_P_CHANNEL_WAIT_CYCLE_OFFSET 0

#define CPU_CLUSTER_CFG_FCM_P_CHANNEL_WAIT_CYCLE_DSLP_LEN    16
#define CPU_CLUSTER_CFG_FCM_P_CHANNEL_WAIT_CYCLE_DSLP_OFFSET 16
#define CPU_CLUSTER_CFG_FCM_P_CHANNEL_WAIT_CYCLE_SD_LEN      16
#define CPU_CLUSTER_CFG_FCM_P_CHANNEL_WAIT_CYCLE_SD_OFFSET   0

#define CPU_CLUSTER_CFG_SCLKQREQN_LEN         1
#define CPU_CLUSTER_CFG_SCLKQREQN_OFFSET      15
#define CPU_CLUSTER_CFG_SCLKQDENY_LEN         1
#define CPU_CLUSTER_CFG_SCLKQDENY_OFFSET      14
#define CPU_CLUSTER_CFG_SCLKQACTIVE_LEN       1
#define CPU_CLUSTER_CFG_SCLKQACTIVE_OFFSET    13
#define CPU_CLUSTER_CFG_SCLKQACCEPTN_LEN      1
#define CPU_CLUSTER_CFG_SCLKQACCEPTN_OFFSET   12
#define CPU_CLUSTER_CFG_PCLKQREQN_LEN         1
#define CPU_CLUSTER_CFG_PCLKQREQN_OFFSET      11
#define CPU_CLUSTER_CFG_PCLKQDENY_LEN         1
#define CPU_CLUSTER_CFG_PCLKQDENY_OFFSET      10
#define CPU_CLUSTER_CFG_PCLKQACTIVE_LEN       1
#define CPU_CLUSTER_CFG_PCLKQACTIVE_OFFSET    9
#define CPU_CLUSTER_CFG_PCLKQACCEPTN_LEN      1
#define CPU_CLUSTER_CFG_PCLKQACCEPTN_OFFSET   8
#define CPU_CLUSTER_CFG_GICCLKQREQN_LEN       1
#define CPU_CLUSTER_CFG_GICCLKQREQN_OFFSET    7
#define CPU_CLUSTER_CFG_GICCLKQDENY_LEN       1
#define CPU_CLUSTER_CFG_GICCLKQDENY_OFFSET    6
#define CPU_CLUSTER_CFG_GICCLKQACTIVE_LEN     1
#define CPU_CLUSTER_CFG_GICCLKQACTIVE_OFFSET  5
#define CPU_CLUSTER_CFG_GICCLKQACCEPTN_LEN    1
#define CPU_CLUSTER_CFG_GICCLKQACCEPTN_OFFSET 4
#define CPU_CLUSTER_CFG_ATCLKQREQN_LEN        1
#define CPU_CLUSTER_CFG_ATCLKQREQN_OFFSET     3
#define CPU_CLUSTER_CFG_ATCLKQDENY_LEN        1
#define CPU_CLUSTER_CFG_ATCLKQDENY_OFFSET     2
#define CPU_CLUSTER_CFG_ATCLKQACTIVE_LEN      1
#define CPU_CLUSTER_CFG_ATCLKQACTIVE_OFFSET   1
#define CPU_CLUSTER_CFG_ATCLKQACCEPTN_LEN     1
#define CPU_CLUSTER_CFG_ATCLKQACCEPTN_OFFSET  0

#define CPU_CLUSTER_CFG_L3_IDLE_WFE_LEN           1
#define CPU_CLUSTER_CFG_L3_IDLE_WFE_OFFSET        26
#define CPU_CLUSTER_CFG_L3_IDLE_WFI_LEN           1
#define CPU_CLUSTER_CFG_L3_IDLE_WFI_OFFSET        25
#define CPU_CLUSTER_CFG_FCM_CAN_POWER_DOWN_LEN    1
#define CPU_CLUSTER_CFG_FCM_CAN_POWER_DOWN_OFFSET 24
#define CPU_CLUSTER_CFG_STANDBYWFE_LEN            8
#define CPU_CLUSTER_CFG_STANDBYWFE_OFFSET         16
#define CPU_CLUSTER_CFG_STANDBYWFI_VDM_LEN        8
#define CPU_CLUSTER_CFG_STANDBYWFI_VDM_OFFSET     8
#define CPU_CLUSTER_CFG_STANDBYWFI_PDC_LEN        8
#define CPU_CLUSTER_CFG_STANDBYWFI_PDC_OFFSET     0

#define CPU_CLUSTER_CFG_FORCED_ON_SFONLY_TO_ON_COMPLETED_LEN    1
#define CPU_CLUSTER_CFG_FORCED_ON_SFONLY_TO_ON_COMPLETED_OFFSET 31
#define CPU_CLUSTER_CFG_CLUSTER_CAN_POWER_DOWN_LEN              1
#define CPU_CLUSTER_CFG_CLUSTER_CAN_POWER_DOWN_OFFSET           28
#define CPU_CLUSTER_CFG_CLUSTER_PDENY_TO_SYS_LEN                1
#define CPU_CLUSTER_CFG_CLUSTER_PDENY_TO_SYS_OFFSET             24
#define CPU_CLUSTER_CFG_CLUSTER_PACCEPT_TO_SYS_LEN              1
#define CPU_CLUSTER_CFG_CLUSTER_PACCEPT_TO_SYS_OFFSET           20
#define CPU_CLUSTER_CFG_CLUSTER_PACTIVE_TO_SYS_LEN              20
#define CPU_CLUSTER_CFG_CLUSTER_PACTIVE_TO_SYS_OFFSET           0

#define CPU_CLUSTER_CFG_CORE0_CAN_POWER_DOWN_LEN    1
#define CPU_CLUSTER_CFG_CORE0_CAN_POWER_DOWN_OFFSET 28
#define CPU_CLUSTER_CFG_CORE0_PDENY_TO_SYS_LEN      1
#define CPU_CLUSTER_CFG_CORE0_PDENY_TO_SYS_OFFSET   24
#define CPU_CLUSTER_CFG_CORE0_PACCEPT_TO_SYS_LEN    1
#define CPU_CLUSTER_CFG_CORE0_PACCEPT_TO_SYS_OFFSET 20
#define CPU_CLUSTER_CFG_CORE0_PACTIVE_TO_SYS_LEN    18
#define CPU_CLUSTER_CFG_CORE0_PACTIVE_TO_SYS_OFFSET 0

#define CPU_CLUSTER_CFG_CORE1_CAN_POWER_DOWN_LEN    1
#define CPU_CLUSTER_CFG_CORE1_CAN_POWER_DOWN_OFFSET 28
#define CPU_CLUSTER_CFG_CORE1_PDENY_TO_SYS_LEN      1
#define CPU_CLUSTER_CFG_CORE1_PDENY_TO_SYS_OFFSET   24
#define CPU_CLUSTER_CFG_CORE1_PACCEPT_TO_SYS_LEN    1
#define CPU_CLUSTER_CFG_CORE1_PACCEPT_TO_SYS_OFFSET 20
#define CPU_CLUSTER_CFG_CORE1_PACTIVE_TO_SYS_LEN    18
#define CPU_CLUSTER_CFG_CORE1_PACTIVE_TO_SYS_OFFSET 0

#define CPU_CLUSTER_CFG_CORE2_CAN_POWER_DOWN_LEN    1
#define CPU_CLUSTER_CFG_CORE2_CAN_POWER_DOWN_OFFSET 28
#define CPU_CLUSTER_CFG_CORE2_PDENY_TO_SYS_LEN      1
#define CPU_CLUSTER_CFG_CORE2_PDENY_TO_SYS_OFFSET   24
#define CPU_CLUSTER_CFG_CORE2_PACCEPT_TO_SYS_LEN    1
#define CPU_CLUSTER_CFG_CORE2_PACCEPT_TO_SYS_OFFSET 20
#define CPU_CLUSTER_CFG_CORE2_PACTIVE_TO_SYS_LEN    18
#define CPU_CLUSTER_CFG_CORE2_PACTIVE_TO_SYS_OFFSET 0

#define CPU_CLUSTER_CFG_CORE3_CAN_POWER_DOWN_LEN    1
#define CPU_CLUSTER_CFG_CORE3_CAN_POWER_DOWN_OFFSET 28
#define CPU_CLUSTER_CFG_CORE3_PDENY_TO_SYS_LEN      1
#define CPU_CLUSTER_CFG_CORE3_PDENY_TO_SYS_OFFSET   24
#define CPU_CLUSTER_CFG_CORE3_PACCEPT_TO_SYS_LEN    1
#define CPU_CLUSTER_CFG_CORE3_PACCEPT_TO_SYS_OFFSET 20
#define CPU_CLUSTER_CFG_CORE3_PACTIVE_TO_SYS_LEN    18
#define CPU_CLUSTER_CFG_CORE3_PACTIVE_TO_SYS_OFFSET 0

#define CPU_CLUSTER_CFG_CORE4_CAN_POWER_DOWN_LEN    1
#define CPU_CLUSTER_CFG_CORE4_CAN_POWER_DOWN_OFFSET 28
#define CPU_CLUSTER_CFG_CORE4_PDENY_TO_SYS_LEN      1
#define CPU_CLUSTER_CFG_CORE4_PDENY_TO_SYS_OFFSET   24
#define CPU_CLUSTER_CFG_CORE4_PACCEPT_TO_SYS_LEN    1
#define CPU_CLUSTER_CFG_CORE4_PACCEPT_TO_SYS_OFFSET 20
#define CPU_CLUSTER_CFG_CORE4_PACTIVE_TO_SYS_LEN    18
#define CPU_CLUSTER_CFG_CORE4_PACTIVE_TO_SYS_OFFSET 0

#define CPU_CLUSTER_CFG_CORE5_CAN_POWER_DOWN_LEN    1
#define CPU_CLUSTER_CFG_CORE5_CAN_POWER_DOWN_OFFSET 28
#define CPU_CLUSTER_CFG_CORE5_PDENY_TO_SYS_LEN      1
#define CPU_CLUSTER_CFG_CORE5_PDENY_TO_SYS_OFFSET   24
#define CPU_CLUSTER_CFG_CORE5_PACCEPT_TO_SYS_LEN    1
#define CPU_CLUSTER_CFG_CORE5_PACCEPT_TO_SYS_OFFSET 20
#define CPU_CLUSTER_CFG_CORE5_PACTIVE_TO_SYS_LEN    18
#define CPU_CLUSTER_CFG_CORE5_PACTIVE_TO_SYS_OFFSET 0

#define CPU_CLUSTER_CFG_CORE6_CAN_POWER_DOWN_LEN    1
#define CPU_CLUSTER_CFG_CORE6_CAN_POWER_DOWN_OFFSET 28
#define CPU_CLUSTER_CFG_CORE6_PDENY_TO_SYS_LEN      1
#define CPU_CLUSTER_CFG_CORE6_PDENY_TO_SYS_OFFSET   24
#define CPU_CLUSTER_CFG_CORE6_PACCEPT_TO_SYS_LEN    1
#define CPU_CLUSTER_CFG_CORE6_PACCEPT_TO_SYS_OFFSET 20
#define CPU_CLUSTER_CFG_CORE6_PACTIVE_TO_SYS_LEN    18
#define CPU_CLUSTER_CFG_CORE6_PACTIVE_TO_SYS_OFFSET 0

#define CPU_CLUSTER_CFG_CORE7_CAN_POWER_DOWN_LEN    1
#define CPU_CLUSTER_CFG_CORE7_CAN_POWER_DOWN_OFFSET 28
#define CPU_CLUSTER_CFG_CORE7_PDENY_TO_SYS_LEN      1
#define CPU_CLUSTER_CFG_CORE7_PDENY_TO_SYS_OFFSET   24
#define CPU_CLUSTER_CFG_CORE7_PACCEPT_TO_SYS_LEN    1
#define CPU_CLUSTER_CFG_CORE7_PACCEPT_TO_SYS_OFFSET 20
#define CPU_CLUSTER_CFG_CORE7_PACTIVE_TO_SYS_LEN    18
#define CPU_CLUSTER_CFG_CORE7_PACTIVE_TO_SYS_OFFSET 0

#define CPU_CLUSTER_CFG_CLUSTERPACCTIVE_LEN    20
#define CPU_CLUSTER_CFG_CLUSTERPACCTIVE_OFFSET 12
#define CPU_CLUSTER_CFG_CLUSTERPSTATE_LEN      7
#define CPU_CLUSTER_CFG_CLUSTERPSTATE_OFFSET   4
#define CPU_CLUSTER_CFG_CLUSTERPREQ_LEN        1
#define CPU_CLUSTER_CFG_CLUSTERPREQ_OFFSET     2
#define CPU_CLUSTER_CFG_CLUSTERPDENY_LEN       1
#define CPU_CLUSTER_CFG_CLUSTERPDENY_OFFSET    1
#define CPU_CLUSTER_CFG_CLUSTERPACCEPT_LEN     1
#define CPU_CLUSTER_CFG_CLUSTERPACCEPT_OFFSET  0

#define CPU_CLUSTER_CFG_COREPACTIVE0_LEN    18
#define CPU_CLUSTER_CFG_COREPACTIVE0_OFFSET 12
#define CPU_CLUSTER_CFG_COREPSTATE0_LEN     6
#define CPU_CLUSTER_CFG_COREPSTATE0_OFFSET  4
#define CPU_CLUSTER_CFG_COREPREQ0_LEN       1
#define CPU_CLUSTER_CFG_COREPREQ0_OFFSET    2
#define CPU_CLUSTER_CFG_COREPDENY0_LEN      1
#define CPU_CLUSTER_CFG_COREPDENY0_OFFSET   1
#define CPU_CLUSTER_CFG_COREPACCEPT0_LEN    1
#define CPU_CLUSTER_CFG_COREPACCEPT0_OFFSET 0

#define CPU_CLUSTER_CFG_COREPACTIVE1_LEN    18
#define CPU_CLUSTER_CFG_COREPACTIVE1_OFFSET 12
#define CPU_CLUSTER_CFG_COREPSTATE1_LEN     6
#define CPU_CLUSTER_CFG_COREPSTATE1_OFFSET  4
#define CPU_CLUSTER_CFG_COREPREQ1_LEN       1
#define CPU_CLUSTER_CFG_COREPREQ1_OFFSET    2
#define CPU_CLUSTER_CFG_COREPDENY1_LEN      1
#define CPU_CLUSTER_CFG_COREPDENY1_OFFSET   1
#define CPU_CLUSTER_CFG_COREPACCEPT1_LEN    1
#define CPU_CLUSTER_CFG_COREPACCEPT1_OFFSET 0

#define CPU_CLUSTER_CFG_COREPACTIVE2_LEN    18
#define CPU_CLUSTER_CFG_COREPACTIVE2_OFFSET 12
#define CPU_CLUSTER_CFG_COREPSTATE2_LEN     6
#define CPU_CLUSTER_CFG_COREPSTATE2_OFFSET  4
#define CPU_CLUSTER_CFG_COREPREQ2_LEN       1
#define CPU_CLUSTER_CFG_COREPREQ2_OFFSET    2
#define CPU_CLUSTER_CFG_COREPDENY2_LEN      1
#define CPU_CLUSTER_CFG_COREPDENY2_OFFSET   1
#define CPU_CLUSTER_CFG_COREPACCEPT2_LEN    1
#define CPU_CLUSTER_CFG_COREPACCEPT2_OFFSET 0

#define CPU_CLUSTER_CFG_COREPACTIVE3_LEN    18
#define CPU_CLUSTER_CFG_COREPACTIVE3_OFFSET 12
#define CPU_CLUSTER_CFG_COREPSTATE3_LEN     6
#define CPU_CLUSTER_CFG_COREPSTATE3_OFFSET  4
#define CPU_CLUSTER_CFG_COREPREQ3_LEN       1
#define CPU_CLUSTER_CFG_COREPREQ3_OFFSET    2
#define CPU_CLUSTER_CFG_COREPDENY3_LEN      1
#define CPU_CLUSTER_CFG_COREPDENY3_OFFSET   1
#define CPU_CLUSTER_CFG_COREPACCEPT3_LEN    1
#define CPU_CLUSTER_CFG_COREPACCEPT3_OFFSET 0

#define CPU_CLUSTER_CFG_COREPACTIVE4_LEN    18
#define CPU_CLUSTER_CFG_COREPACTIVE4_OFFSET 12
#define CPU_CLUSTER_CFG_COREPSTATE4_LEN     6
#define CPU_CLUSTER_CFG_COREPSTATE4_OFFSET  4
#define CPU_CLUSTER_CFG_COREPREQ4_LEN       1
#define CPU_CLUSTER_CFG_COREPREQ4_OFFSET    2
#define CPU_CLUSTER_CFG_COREPDENY4_LEN      1
#define CPU_CLUSTER_CFG_COREPDENY4_OFFSET   1
#define CPU_CLUSTER_CFG_COREPACCEPT4_LEN    1
#define CPU_CLUSTER_CFG_COREPACCEPT4_OFFSET 0

#define CPU_CLUSTER_CFG_COREPACTIVE5_LEN    18
#define CPU_CLUSTER_CFG_COREPACTIVE5_OFFSET 12
#define CPU_CLUSTER_CFG_COREPSTATE5_LEN     6
#define CPU_CLUSTER_CFG_COREPSTATE5_OFFSET  4
#define CPU_CLUSTER_CFG_COREPREQ5_LEN       1
#define CPU_CLUSTER_CFG_COREPREQ5_OFFSET    2
#define CPU_CLUSTER_CFG_COREPDENY5_LEN      1
#define CPU_CLUSTER_CFG_COREPDENY5_OFFSET   1
#define CPU_CLUSTER_CFG_COREPACCEPT5_LEN    1
#define CPU_CLUSTER_CFG_COREPACCEPT5_OFFSET 0

#define CPU_CLUSTER_CFG_COREPACTIVE6_LEN    18
#define CPU_CLUSTER_CFG_COREPACTIVE6_OFFSET 12
#define CPU_CLUSTER_CFG_COREPSTATE6_LEN     6
#define CPU_CLUSTER_CFG_COREPSTATE6_OFFSET  4
#define CPU_CLUSTER_CFG_COREPREQ6_LEN       1
#define CPU_CLUSTER_CFG_COREPREQ6_OFFSET    2
#define CPU_CLUSTER_CFG_COREPDENY6_LEN      1
#define CPU_CLUSTER_CFG_COREPDENY6_OFFSET   1
#define CPU_CLUSTER_CFG_COREPACCEPT6_LEN    1
#define CPU_CLUSTER_CFG_COREPACCEPT6_OFFSET 0

#define CPU_CLUSTER_CFG_COREPACTIVE7_LEN    18
#define CPU_CLUSTER_CFG_COREPACTIVE7_OFFSET 12
#define CPU_CLUSTER_CFG_COREPSTATE7_LEN     6
#define CPU_CLUSTER_CFG_COREPSTATE7_OFFSET  4
#define CPU_CLUSTER_CFG_COREPREQ7_LEN       1
#define CPU_CLUSTER_CFG_COREPREQ7_OFFSET    2
#define CPU_CLUSTER_CFG_COREPDENY7_LEN      1
#define CPU_CLUSTER_CFG_COREPDENY7_OFFSET   1
#define CPU_CLUSTER_CFG_COREPACCEPT7_LEN    1
#define CPU_CLUSTER_CFG_COREPACCEPT7_OFFSET 0

#define CPU_CLUSTER_CFG_CORE1_PCHANNEL_DEBUG_INFO_LEN    16
#define CPU_CLUSTER_CFG_CORE1_PCHANNEL_DEBUG_INFO_OFFSET 16
#define CPU_CLUSTER_CFG_CORE0_PCHANNEL_DEBUG_INFO_LEN    16
#define CPU_CLUSTER_CFG_CORE0_PCHANNEL_DEBUG_INFO_OFFSET 0

#define CPU_CLUSTER_CFG_CORE3_PCHANNEL_DEBUG_INFO_LEN    16
#define CPU_CLUSTER_CFG_CORE3_PCHANNEL_DEBUG_INFO_OFFSET 16
#define CPU_CLUSTER_CFG_CORE2_PCHANNEL_DEBUG_INFO_LEN    16
#define CPU_CLUSTER_CFG_CORE2_PCHANNEL_DEBUG_INFO_OFFSET 0

#define CPU_CLUSTER_CFG_CORE5_PCHANNEL_DEBUG_INFO_LEN    16
#define CPU_CLUSTER_CFG_CORE5_PCHANNEL_DEBUG_INFO_OFFSET 16
#define CPU_CLUSTER_CFG_CORE4_PCHANNEL_DEBUG_INFO_LEN    16
#define CPU_CLUSTER_CFG_CORE4_PCHANNEL_DEBUG_INFO_OFFSET 0

#define CPU_CLUSTER_CFG_CORE7_PCHANNEL_DEBUG_INFO_LEN    16
#define CPU_CLUSTER_CFG_CORE7_PCHANNEL_DEBUG_INFO_OFFSET 16
#define CPU_CLUSTER_CFG_CORE6_PCHANNEL_DEBUG_INFO_LEN    16
#define CPU_CLUSTER_CFG_CORE6_PCHANNEL_DEBUG_INFO_OFFSET 0

#define CPU_CLUSTER_CFG_FCM_PCHANNEL_DEBUG_INFO_LEN    32
#define CPU_CLUSTER_CFG_FCM_PCHANNEL_DEBUG_INFO_OFFSET 0

#define CPU_CLUSTER_CFG_CORE7_PWR_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE7_PWR_EN_OFFSET 31
#define CPU_CLUSTER_CFG_CORE6_PWR_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE6_PWR_EN_OFFSET 30
#define CPU_CLUSTER_CFG_CORE5_PWR_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE5_PWR_EN_OFFSET 29
#define CPU_CLUSTER_CFG_CORE4_PWR_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE4_PWR_EN_OFFSET 28
#define CPU_CLUSTER_CFG_CORE3_PWR_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE3_PWR_EN_OFFSET 27
#define CPU_CLUSTER_CFG_CORE2_PWR_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE2_PWR_EN_OFFSET 26
#define CPU_CLUSTER_CFG_CORE1_PWR_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE1_PWR_EN_OFFSET 25
#define CPU_CLUSTER_CFG_CORE0_PWR_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE0_PWR_EN_OFFSET 24
#define CPU_CLUSTER_CFG_CORE7_ISO_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE7_ISO_EN_OFFSET 23
#define CPU_CLUSTER_CFG_CORE6_ISO_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE6_ISO_EN_OFFSET 22
#define CPU_CLUSTER_CFG_CORE5_ISO_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE5_ISO_EN_OFFSET 21
#define CPU_CLUSTER_CFG_CORE4_ISO_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE4_ISO_EN_OFFSET 20
#define CPU_CLUSTER_CFG_CORE3_ISO_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE3_ISO_EN_OFFSET 19
#define CPU_CLUSTER_CFG_CORE2_ISO_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE2_ISO_EN_OFFSET 18
#define CPU_CLUSTER_CFG_CORE1_ISO_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE1_ISO_EN_OFFSET 17
#define CPU_CLUSTER_CFG_CORE0_ISO_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE0_ISO_EN_OFFSET 16
#define CPU_CLUSTER_CFG_CORE7_DBG_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE7_DBG_EN_OFFSET 15
#define CPU_CLUSTER_CFG_CORE6_DBG_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE6_DBG_EN_OFFSET 14
#define CPU_CLUSTER_CFG_CORE5_DBG_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE5_DBG_EN_OFFSET 13
#define CPU_CLUSTER_CFG_CORE4_DBG_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE4_DBG_EN_OFFSET 12
#define CPU_CLUSTER_CFG_CORE3_DBG_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE3_DBG_EN_OFFSET 11
#define CPU_CLUSTER_CFG_CORE2_DBG_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE2_DBG_EN_OFFSET 10
#define CPU_CLUSTER_CFG_CORE1_DBG_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE1_DBG_EN_OFFSET 9
#define CPU_CLUSTER_CFG_CORE0_DBG_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE0_DBG_EN_OFFSET 8
#define CPU_CLUSTER_CFG_CORE7_PDC_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE7_PDC_EN_OFFSET 7
#define CPU_CLUSTER_CFG_CORE6_PDC_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE6_PDC_EN_OFFSET 6
#define CPU_CLUSTER_CFG_CORE5_PDC_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE5_PDC_EN_OFFSET 5
#define CPU_CLUSTER_CFG_CORE4_PDC_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE4_PDC_EN_OFFSET 4
#define CPU_CLUSTER_CFG_CORE3_PDC_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE3_PDC_EN_OFFSET 3
#define CPU_CLUSTER_CFG_CORE2_PDC_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE2_PDC_EN_OFFSET 2
#define CPU_CLUSTER_CFG_CORE1_PDC_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE1_PDC_EN_OFFSET 1
#define CPU_CLUSTER_CFG_CORE0_PDC_EN_LEN    1
#define CPU_CLUSTER_CFG_CORE0_PDC_EN_OFFSET 0

#define CPU_CLUSTER_CFG_CORE7_PWRUP_REQ_LEN    1
#define CPU_CLUSTER_CFG_CORE7_PWRUP_REQ_OFFSET 7
#define CPU_CLUSTER_CFG_CORE6_PWRUP_REQ_LEN    1
#define CPU_CLUSTER_CFG_CORE6_PWRUP_REQ_OFFSET 6
#define CPU_CLUSTER_CFG_CORE5_PWRUP_REQ_LEN    1
#define CPU_CLUSTER_CFG_CORE5_PWRUP_REQ_OFFSET 5
#define CPU_CLUSTER_CFG_CORE4_PWRUP_REQ_LEN    1
#define CPU_CLUSTER_CFG_CORE4_PWRUP_REQ_OFFSET 4
#define CPU_CLUSTER_CFG_CORE3_PWRUP_REQ_LEN    1
#define CPU_CLUSTER_CFG_CORE3_PWRUP_REQ_OFFSET 3
#define CPU_CLUSTER_CFG_CORE2_PWRUP_REQ_LEN    1
#define CPU_CLUSTER_CFG_CORE2_PWRUP_REQ_OFFSET 2
#define CPU_CLUSTER_CFG_CORE1_PWRUP_REQ_LEN    1
#define CPU_CLUSTER_CFG_CORE1_PWRUP_REQ_OFFSET 1
#define CPU_CLUSTER_CFG_CORE0_PWRUP_REQ_LEN    1
#define CPU_CLUSTER_CFG_CORE0_PWRUP_REQ_OFFSET 0

#define CPU_CLUSTER_CFG_CORE7_PWRDN_REQ_LEN    1
#define CPU_CLUSTER_CFG_CORE7_PWRDN_REQ_OFFSET 7
#define CPU_CLUSTER_CFG_CORE6_PWRDN_REQ_LEN    1
#define CPU_CLUSTER_CFG_CORE6_PWRDN_REQ_OFFSET 6
#define CPU_CLUSTER_CFG_CORE5_PWRDN_REQ_LEN    1
#define CPU_CLUSTER_CFG_CORE5_PWRDN_REQ_OFFSET 5
#define CPU_CLUSTER_CFG_CORE4_PWRDN_REQ_LEN    1
#define CPU_CLUSTER_CFG_CORE4_PWRDN_REQ_OFFSET 4
#define CPU_CLUSTER_CFG_CORE3_PWRDN_REQ_LEN    1
#define CPU_CLUSTER_CFG_CORE3_PWRDN_REQ_OFFSET 3
#define CPU_CLUSTER_CFG_CORE2_PWRDN_REQ_LEN    1
#define CPU_CLUSTER_CFG_CORE2_PWRDN_REQ_OFFSET 2
#define CPU_CLUSTER_CFG_CORE1_PWRDN_REQ_LEN    1
#define CPU_CLUSTER_CFG_CORE1_PWRDN_REQ_OFFSET 1
#define CPU_CLUSTER_CFG_CORE0_PWRDN_REQ_LEN    1
#define CPU_CLUSTER_CFG_CORE0_PWRDN_REQ_OFFSET 0

#define CPU_CLUSTER_CFG_CORE7_PMCTRL_SEL_LEN    1
#define CPU_CLUSTER_CFG_CORE7_PMCTRL_SEL_OFFSET 7
#define CPU_CLUSTER_CFG_CORE6_PMCTRL_SEL_LEN    1
#define CPU_CLUSTER_CFG_CORE6_PMCTRL_SEL_OFFSET 6
#define CPU_CLUSTER_CFG_CORE5_PMCTRL_SEL_LEN    1
#define CPU_CLUSTER_CFG_CORE5_PMCTRL_SEL_OFFSET 5
#define CPU_CLUSTER_CFG_CORE4_PMCTRL_SEL_LEN    1
#define CPU_CLUSTER_CFG_CORE4_PMCTRL_SEL_OFFSET 4
#define CPU_CLUSTER_CFG_CORE3_PMCTRL_SEL_LEN    1
#define CPU_CLUSTER_CFG_CORE3_PMCTRL_SEL_OFFSET 3
#define CPU_CLUSTER_CFG_CORE2_PMCTRL_SEL_LEN    1
#define CPU_CLUSTER_CFG_CORE2_PMCTRL_SEL_OFFSET 2
#define CPU_CLUSTER_CFG_CORE1_PMCTRL_SEL_LEN    1
#define CPU_CLUSTER_CFG_CORE1_PMCTRL_SEL_OFFSET 1
#define CPU_CLUSTER_CFG_CORE0_PMCTRL_SEL_LEN    1
#define CPU_CLUSTER_CFG_CORE0_PMCTRL_SEL_OFFSET 0

#define CPU_CLUSTER_CFG_CORE7_PWRUP_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE7_PWRUP_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE6_PWRUP_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE6_PWRUP_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE5_PWRUP_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE5_PWRUP_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE4_PWRUP_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE4_PWRUP_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE3_PWRUP_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE3_PWRUP_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE2_PWRUP_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE2_PWRUP_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE1_PWRUP_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE1_PWRUP_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE0_PWRUP_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE0_PWRUP_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE7_PWRDN_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE7_PWRDN_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE6_PWRDN_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE6_PWRDN_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE5_PWRDN_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE5_PWRDN_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE4_PWRDN_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE4_PWRDN_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE3_PWRDN_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE3_PWRDN_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE2_PWRDN_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE2_PWRDN_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE1_PWRDN_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE1_PWRDN_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE0_PWRDN_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE0_PWRDN_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE7_ISO_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE7_ISO_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE6_ISO_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE6_ISO_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE5_ISO_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE5_ISO_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE4_ISO_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE4_ISO_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE3_ISO_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE3_ISO_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE2_ISO_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE2_ISO_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE1_ISO_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE1_ISO_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE0_ISO_TIME_LEN    16
#define CPU_CLUSTER_CFG_CORE0_ISO_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE7_RST_TIME_LEN    3
#define CPU_CLUSTER_CFG_CORE7_RST_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE6_RST_TIME_LEN    3
#define CPU_CLUSTER_CFG_CORE6_RST_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE5_RST_TIME_LEN    3
#define CPU_CLUSTER_CFG_CORE5_RST_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE4_RST_TIME_LEN    3
#define CPU_CLUSTER_CFG_CORE4_RST_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE3_RST_TIME_LEN    3
#define CPU_CLUSTER_CFG_CORE3_RST_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE2_RST_TIME_LEN    3
#define CPU_CLUSTER_CFG_CORE2_RST_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE1_RST_TIME_LEN    3
#define CPU_CLUSTER_CFG_CORE1_RST_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE0_RST_TIME_LEN    3
#define CPU_CLUSTER_CFG_CORE0_RST_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE7_URST_TIME_LEN    6
#define CPU_CLUSTER_CFG_CORE7_URST_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE6_URST_TIME_LEN    6
#define CPU_CLUSTER_CFG_CORE6_URST_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE5_URST_TIME_LEN    6
#define CPU_CLUSTER_CFG_CORE5_URST_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE4_URST_TIME_LEN    6
#define CPU_CLUSTER_CFG_CORE4_URST_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE3_URST_TIME_LEN    6
#define CPU_CLUSTER_CFG_CORE3_URST_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE2_URST_TIME_LEN    6
#define CPU_CLUSTER_CFG_CORE2_URST_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE1_URST_TIME_LEN    6
#define CPU_CLUSTER_CFG_CORE1_URST_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE0_URST_TIME_LEN    6
#define CPU_CLUSTER_CFG_CORE0_URST_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE7_DBG_TIME_LEN    4
#define CPU_CLUSTER_CFG_CORE7_DBG_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE6_DBG_TIME_LEN    4
#define CPU_CLUSTER_CFG_CORE6_DBG_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE5_DBG_TIME_LEN    4
#define CPU_CLUSTER_CFG_CORE5_DBG_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE4_DBG_TIME_LEN    4
#define CPU_CLUSTER_CFG_CORE4_DBG_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE3_DBG_TIME_LEN    4
#define CPU_CLUSTER_CFG_CORE3_DBG_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE2_DBG_TIME_LEN    4
#define CPU_CLUSTER_CFG_CORE2_DBG_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE1_DBG_TIME_LEN    4
#define CPU_CLUSTER_CFG_CORE1_DBG_TIME_OFFSET 16
#define CPU_CLUSTER_CFG_CORE0_DBG_TIME_LEN    4
#define CPU_CLUSTER_CFG_CORE0_DBG_TIME_OFFSET 0

#define CPU_CLUSTER_CFG_CORE0_PWRSTAT_LEN    4
#define CPU_CLUSTER_CFG_CORE0_PWRSTAT_OFFSET 28
#define CPU_CLUSTER_CFG_CORE1_PWRSTAT_LEN    4
#define CPU_CLUSTER_CFG_CORE1_PWRSTAT_OFFSET 24
#define CPU_CLUSTER_CFG_CORE2_PWRSTAT_LEN    4
#define CPU_CLUSTER_CFG_CORE2_PWRSTAT_OFFSET 20
#define CPU_CLUSTER_CFG_CORE3_PWRSTAT_LEN    4
#define CPU_CLUSTER_CFG_CORE3_PWRSTAT_OFFSET 16
#define CPU_CLUSTER_CFG_CORE4_PWRSTAT_LEN    4
#define CPU_CLUSTER_CFG_CORE4_PWRSTAT_OFFSET 12
#define CPU_CLUSTER_CFG_CORE5_PWRSTAT_LEN    4
#define CPU_CLUSTER_CFG_CORE5_PWRSTAT_OFFSET 8
#define CPU_CLUSTER_CFG_CORE6_PWRSTAT_LEN    4
#define CPU_CLUSTER_CFG_CORE6_PWRSTAT_OFFSET 4
#define CPU_CLUSTER_CFG_CORE7_PWRSTAT_LEN    4
#define CPU_CLUSTER_CFG_CORE7_PWRSTAT_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_CFG_VERSION0_LEN    32
#define CPU_CLUSTER_CFG_CPU_CFG_VERSION0_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_CFG_MAGIC_WORD_LEN    32
#define CPU_CLUSTER_CFG_CPU_CFG_MAGIC_WORD_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_CFG_ECO_CFG0_LEN    32
#define CPU_CLUSTER_CFG_CPU_CFG_ECO_CFG0_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_CFG_ECO_CFG1_LEN    32
#define CPU_CLUSTER_CFG_CPU_CFG_ECO_CFG1_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_CFG_ECO_CFG2_LEN    32
#define CPU_CLUSTER_CFG_CPU_CFG_ECO_CFG2_OFFSET 0

#define CPU_CLUSTER_CFG_CPU_CFG_ECO_CFG3_LEN    32
#define CPU_CLUSTER_CFG_CPU_CFG_ECO_CFG3_OFFSET 0

#define CPU_CLUSTER_CFG_SYSCTRL_LOCK_LEN    32
#define CPU_CLUSTER_CFG_SYSCTRL_LOCK_OFFSET 0

#define CPU_CLUSTER_CFG_SYSCTRL_UNLOCK_LEN    32
#define CPU_CLUSTER_CFG_SYSCTRL_UNLOCK_OFFSET 0

#define CPU_CLUSTER_CFG_ECO_RSV0_LEN    32
#define CPU_CLUSTER_CFG_ECO_RSV0_OFFSET 0

#define CPU_CLUSTER_CFG_ECO_RSV1_LEN    32
#define CPU_CLUSTER_CFG_ECO_RSV1_OFFSET 0

#define CPU_CLUSTER_CFG_ECO_RSV2_LEN    32
#define CPU_CLUSTER_CFG_ECO_RSV2_OFFSET 0

#define CPU_CLUSTER_CFG_ECO_RSV3_LEN    32
#define CPU_CLUSTER_CFG_ECO_RSV3_OFFSET 0

#define CPU_CLUSTER_CFG_PROTOTYPE_CLK_LEN    32
#define CPU_CLUSTER_CFG_PROTOTYPE_CLK_OFFSET 0

#define CPU_CLUSTER_CFG_PROTOTYPE_RST_N_LEN    32
#define CPU_CLUSTER_CFG_PROTOTYPE_RST_N_OFFSET 0

#define CPU_CLUSTER_CFG_FPGA_VERI_NUM_LEN    32
#define CPU_CLUSTER_CFG_FPGA_VERI_NUM_OFFSET 0

#endif // __CPU_CLUSTER_CFG_REG_OFFSET_FIELD_H__
